1. Field
The present invention relates to a CMOS differential logic circuit, and more particularly, to a CMOS differential logic circuit using a voltage boosting technique, which is capable of improving operating speed and energy efficiency in a low-source-voltage environment in such a way as to supply a source voltage boosted by the capacitive coupling of a MOS transistor for transferring a signal from an input terminal to an output terminal.
2. Description of the Related Art
The increasing interest in energy-efficient design is provoking a growing need for portable devices that consume energy efficiently.
Since most energy consumption of modern digital CMOS circuits is historically attributable to switching energy dependent on a source voltage, voltage scaling is an effective way to minimize the overall energy consumption of a system-on-chip.
In extreme cases, circuits can be made to operate in a sub-threshold region for maximum energy efficiency. This approach is limited to use only in low-end designs in which operating speed is a secondary concern because of severe speed degradation, attributable to the low switching current, and great performance variability due to changes in process, temperature, and threshold voltage.
In contrast, for medium- and high-end circuits, where both speed performance and energy efficiency are important, extreme voltage scaling is not acceptable, and instead, a near-threshold voltage design is more suitable for achieving relatively high energy efficiency without severe speed degradation.
FIG. 1 is a circuit diagram of a conventional differential cascode voltage switch (DCVS) circuit. The DCVS circuit includes first and second PMOS transistors MP1 and MP2, a differential logic unit 10, a first NMOS transistor MN1, and first and second inverters IN1 and IN2.
FIG. 2 is a circuit diagram of a conventional bootstrapped dynamic logic (BDL) circuit. The conventional BDL circuit includes first and second PMOS transistors MP1 and MP2, a differential logic unit 20, a first NMOS transistor MN1, and first and second output units 30 and 40.
The first output unit 30 includes a third inverter IN3, fourth and fifth PMOS transistors MP4 and MP5, a third NMOS transistor MN3, and a first bootstrapped capacitor CB1. The second output unit 40 includes a fourth inverter IN4, sixth and seventh PMOS transistors MP6 and MP7, a fourth NMOS transistor MN4, and a second bootstrapped capacitor C.
The operations of the conventional DCVS circuit and the conventional BDL are described below with reference to FIGS. 1 and 2.
In general, the switching operating speed of a transistor is greatly influenced by the difference between a gate-source voltage VGS and a threshold voltage VTH.
Accordingly, when the source voltage VDD is scaled down, the gate-source voltage VGS drops and the difference between the gate-source voltage VGS and the threshold voltage VTH is gradually reduced because the threshold voltage VTH is fixed. As a result, the operating speed of the transistor is greatly reduced.
That is, in the conventional DCVS circuit of FIG. 1, when the source voltage is scaled down toward the threshold voltage, the operating speed is severely reduced due to the reduction in the overdrive voltage VGS VGS−VTH of the transistor.
As described above, the conventional DCVS circuit can operate at high speed because the number of transistors that form the logic and the magnitude of input capacitance are small. The conventional DCVS circuit, however, is problematic in that, like the existing CMOS logic, the operating speed is greatly reduced when the source voltage VDD is scaled down because the output current is proportional to the supplied source voltage VDD.
In order to overcome this problem, a bootstrapped CMOS large capacitive-load driver circuit was proposed. The bootstrapped CMOS large capacitive-load driver circuit can improve switching speed at low source voltages by allowing the voltage of some internal nodes to be boosted beyond the source voltage.
However, since the circuit is used as a large capacitive-load driver, logic functions cannot be efficiently embedded into the circuit.
In order to overcome this limitation, a bootstrapped dynamic logic (BDL) circuit, such as that shown in FIG. 2 for high-speed logic operations at low source voltage, was proposed.
The conventional BDL circuit includes the first and second output units 30 and 40. Precharge and boosting operations are sequentially performed in the first and second output units 30 and 40 in response to changes in the levels of a clock signal CLK and an input signal supplied to the differential logic unit 20.
That is, the first output units 30 is connected to an output terminal OUT1, precharged in response to a low-level clock signal CLK, and boosted by the capacitive coupling of the first bootstrapped capacitor CB1 in response to a high-level first input signal and the high-level clock signal CLK supplied to the differential logic unit 20.
The second output units 40 is connected to the differential logic unit 20, precharged in response to the low-level clock signal CLK, and boosted by the capacitive coupling of the second bootstrapped capacitor CB2 in response to a second high-level input signal and the high-level clock signal CLK supplied to the differential logic unit 20.
As described above, since the conventional BDL circuit must use two large-capacitive bootstrapped capacitors, the operating speed of this logic style is not improved much due to the addition of the overall latency of the circuit.
Furthermore, the logic composition of this logic style is constrained since this logic style is configured as a single-ended structure.
In addition, although some recent circuit techniques adopting bootstrapped operation have been proposed, they are not all for logic composition. Some are for large capacitance driving.
As described above, the conventional BDL reduces the problems with the existing circuits in which the operating speed is reduced according to the reduction in scale of the source voltage VDD by outputting voltage higher than the source voltage VDD by way of capacitive coupling.
However, the two large-capacitive bootstrapped capacitors must be used in the output terminal of the circuit in order to boost the output voltage, and the size of the transistors that form the logic must be increased in order to rapidly drive the output of this structure. Accordingly, there is a problem in that energy consumption is also increased in proportion thereto.
Meanwhile, the importance of low consumption power design has greatly increased due to the growth of portable electronic devices that employ limited energy sources such as batteries.
As an effective design technique for low power consumption, there is a method of scaling down source voltage VDD. When the source voltage VDD is scaled down, the energy consumption of a system can be reduced because the energy consumption of transistors that form the system is reduced in proportion to the square of the source voltage VDD.
When the source voltage VDD is scaled down, however, there is a problem in that the operating speed of the system is reduced because the operating speed of the transistor is sharply reduced.
In order to solve this problem, there is a need for a circuit capable of operating at high speed even at a low source voltage.